This invention relates to a method for manufacturing an LSI (large scale integration) semiconductor device using a polycrystalline silicon layer as an electrode and/or wire.
Especially for large scale integration of an MOS (metal oxide semiconductor) type field-effect transistor (FET), there is known as an advanced technique the silicon gate technology employing a polycrystalline silicon layer as a gate electrode and forming source and drain regions in the self-alignment system.
Such silicon gate technology, however, still involves too many problems to achieve further improved LSI.
Referring now to the drawings of FIGS. 1a to 1e, there will be described the aforesaid problems in connection with a method for manufacturing an LSI n-channel MOS FET, by way of example. As shown in FIG. 1a, a silicon oxide (SiO.sub.2) film 2 with a thickness of approximately 1 .mu.m is formed by selectively oxidizing the surface of a p-type silicon substrate 1, thereby isolating elements from one another. Then, as shown in FIG. 1b, an SiO.sub.2 film 3 as thin as about 700 A to serve as a gate oxide film is formed by oxidizing part of the surface of the substrate 1 which is not covered with the SiO.sub.2 film 2, and a polycrystalline silicon layer 4 with a thickness of about 3,000 A is formed over the whole surface of the SiO.sub.2 film 3.
As shown in FIG. 1b, phosphorus from e.g. POCl.sub.3 as a diffusion source is diffused into the whole surface of the polycrystalline silicon layer 4 at approximately 1,000.degree. C. for about 10 minutes. A polycrystalline silicon layer 4' subjected to such diffusion, having a relatively low resistance, can be used as a gate electrode.
A photo-resist film 5 is formed selectively on the polycrystalline silicon layer 4' doped with the impurity, as shown in FIG. 1c, the polycrystalline silicon layer 4' is plasma-etched for patterning by using e.g. freon plasma, and part of the polycrystalline silicon layer 4' is left to form a gate electrode.
Subsequently, as shown in FIG. 1d, n-type source and drain regions 6 and 7 are formed by removing portions of the 700 A SiO.sub.2 film 3 to form the source and drain regions, also removing the photo-resist film 5, implanting e.g. 150 kev As ion at a rate of 1.times.10.sup.16 /cm.sup.2, and annealing the resultant structure in an N.sub.2 atmosphere at approximately 1,000.degree. C. for about one hour.
Then, as shown in FIG. 1e, a relatively thick or e.g. about 1 .mu.m SiO.sub.2 film 8 is formed all over the surface by the gaseous growth method, contact holes for electrical contact are bored in the SiO.sub.2 film 8, an aluminium layer 9 is formed selectively, an oxide film doped with e.g. phosphorus or PSG film 10 is formed on the Al layer 9, and finally an electrode opening 10a is bored in the PSG film 10.
In the above-mentioned method for manufacturing the MOS FET, the polycrystalline silicon layer 4' used as the gate electrode is a gathering of a great number of small crystalline regions called grains. At the boundaries among these grains, however, there may be caused what is called impurity penetration such that impurity such as phosphorus is diffused abnormally fast at the boundaries among the grains to reach the Si substrates 1 through the about 700 A gate oxide film 3. Moreover, those boundary portions are poor in the masking capability against ion implantation, so that As ion may often be partially implanted in the Si substrate 1 though thin SiO.sub.2 layer 3 in the formation of the source and drain regions 6 and 7 by the ion implantation method as shown in FIG. 1d. Thus, if the impurity with which the polycrystalline silicon layer 4' or the source and drain regions 6 and 7 are doped is introduced into the Si substrate 1 under the gate electrode, the normal operation of the transistor will be impeded.
Further, since the polycrystalline silicon layer 4' used as the gate electrode is a gathering of a great number of small crystalline regions called grains, as described above, exhibiting different crystalline characteristics and uneven impurity distribution, so the etching would often proceed at an extraordinarily high speed along the boundaries among the grains. If such effect is caused, the periphery of the polycrystalline silicon layer 4' to form the gate electorde will possibly be jagged or partially notched. In consequence, the width of the polycrystalline silicon layer 4' partially narrowed to cause a short circuit between the source and drain regions 6 and 7, which will interrupt the operation of the transistor. This phenomenon becomes more distinguished as the width of the polycrystalline silicon 4' is reduced accompanying the large scale integration of semiconductor devices.
The resistance value of the polycrystalline silicon layer 4' to form the electrode, manufactured by the above-mentioned prior art method, is approximately 20.OMEGA./.quadrature.. Although this resistance value may be decreased as the impurity (phosphorus) difusion time increases, it will not be reduced below approximately 20.OMEGA./.quadrature.. This is attributable to a fact that the concentration of phosphorus in the polycrystalline silicon layer cannot exceed the solid solubility. If the thickness of the polycrystalline silicon layer is, for example, double (approx. 6,000 A) in order to lower the resistance value, the resistance value will substantially be halved. The increase in the thickness of the layer will, however, make it hard to achieve accurate patterning, so that such operation cannot be used for a process for forming a fine pattern, in particular. When using the polycrystalline silicon layer as a wire to transmit signals in an LSI, on the other hand, it is necessary that the resistance value of the layer be reduced as low as possible to increase the operating speed of the device. The prior art method has not been able to fulfill these requirements.